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adc

altera_modular_adc v14.1

Parameters CORE_VAR 2 ENABLE_DEBUG 0 MONITOR_COUNT_WIDTH 12 CLOCK_FREQ 50000000 FAMILY MAX10FPGA DEVICE_PART 10M08SAU169C8GES device_partname_fivechar_prefix 10M08 device_adc_type 22 max_adc_count_on_die 1 adc_count_on_device 1 device_power_supply_type 1 ip_is_for_which_adc 1 is_this_first_or_second_adc 1 analog_input_pin_mask 0 hard_pwd 0 clkdiv 2 tsclkdiv 1 tsclksel 1 refsel 1 external_vref 2.5 int_vref_vr 3.0 int_vref_nonvr 2.5 reference_voltage 3.0 prescalar 0 use_tsd false en_tsd_max false tsd_max 125 en_tsd_min false tsd_min 0 use_ch0 true en_thmax_ch0 false thmax_ch0 0.0 en_thmin_ch0 false thmin_ch0 0.0 use_ch1 true en_thmax_ch1 false thmax_ch1 0.0 en_thmin_ch1 false thmin_ch1 0.0 use_ch2 true en_thmax_ch2 false thmax_ch2 0.0 en_thmin_ch2 false thmin_ch2 0.0 use_ch3 true en_thmax_ch3 false thmax_ch3 0.0 en_thmin_ch3 false thmin_ch3 0.0 use_ch4 true en_thmax_ch4 false thmax_ch4 0.0 en_thmin_ch4 false thmin_ch4 0.0 use_ch5 true en_thmax_ch5 false thmax_ch5 0.0 en_thmin_ch5 false thmin_ch5 0.0 use_ch6 true en_thmax_ch6 false thmax_ch6 0.0 en_thmin_ch6 false thmin_ch6 0.0 use_ch7 false en_thmax_ch7 false thmax_ch7 0.0 en_thmin_ch7 false thmin_ch7 0.0 use_ch8 false prescaler_ch8 false en_thmax_ch8 false thmax_ch8 0.0 en_thmin_ch8 false thmin_ch8 0.0 use_ch9 false en_thmax_ch9 false thmax_ch9 0.0 en_thmin_ch9 false thmin_ch9 0.0 use_ch10 false en_thmax_ch10 false thmax_ch10 0.0 en_thmin_ch10 false thmin_ch10 0.0 use_ch11 false en_thmax_ch11 false thmax_ch11 0.0 en_thmin_ch11 false thmin_ch11 0.0 use_ch12 false en_thmax_ch12 false thmax_ch12 0.0 en_thmin_ch12 false thmin_ch12 0.0 use_ch13 false en_thmax_ch13 false thmax_ch13 0.0 en_thmin_ch13 false thmin_ch13 0.0 use_ch14 false en_thmax_ch14 false thmax_ch14 0.0 en_thmin_ch14 false thmin_ch14 0.0 use_ch15 false en_thmax_ch15 false thmax_ch15 0.0 en_thmin_ch15 false thmin_ch15 0.0 use_ch16 false prescaler_ch16 false en_thmax_ch16 false thmax_ch16 0.0 en_thmin_ch16 false thmin_ch16 0.0 seq_order_length 7 seq_order_slot_1 0 seq_order_slot_2 1 seq_order_slot_3 2 seq_order_slot_4 3 seq_order_slot_5 4 seq_order_slot_6 5 seq_order_slot_7 6 seq_order_slot_8 7 seq_order_slot_9 8 seq_order_slot_10 30 seq_order_slot_11 30 seq_order_slot_12 30 seq_order_slot_13 30 seq_order_slot_14 30 seq_order_slot_15 30 seq_order_slot_16 30 seq_order_slot_17 30 seq_order_slot_18 30 seq_order_slot_19 30 seq_order_slot_20 30 seq_order_slot_21 30 seq_order_slot_22 30 seq_order_slot_23 30 seq_order_slot_24 30 seq_order_slot_25 30 seq_order_slot_26 30 seq_order_slot_27 30 seq_order_slot_28 30 seq_order_slot_29 30 seq_order_slot_30 30 seq_order_slot_31 30 seq_order_slot_32 30 seq_order_slot_33 30 seq_order_slot_34 30 seq_order_slot_35 30 seq_order_slot_36 30 seq_order_slot_37 30 seq_order_slot_38 30 seq_order_slot_39 30 seq_order_slot_40 30 seq_order_slot_41 30 seq_order_slot_42 30 seq_order_slot_43 30 seq_order_slot_44 30 seq_order_slot_45 30 seq_order_slot_46 30 seq_order_slot_47 30 seq_order_slot_48 30 seq_order_slot_49 30 seq_order_slot_50 30 seq_order_slot_51 30 seq_order_slot_52 30 seq_order_slot_53 30 seq_order_slot_54 30 seq_order_slot_55 30 seq_order_slot_56 30 seq_order_slot_57 30 seq_order_slot_58 30 seq_order_slot_59 30 seq_order_slot_60 30 seq_order_slot_61 30 seq_order_slot_62 30 seq_order_slot_63 30 seq_order_slot_64 30 AUTO_DEVICE_SPEEDGRADE 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CORE_VARIANT 2 CSD_LENGTH 7 CSD_SLOT_0 0 CSD_SLOT_1 1 CSD_SLOT_10 0 CSD_SLOT_11 0 CSD_SLOT_12 0 CSD_SLOT_13 0 CSD_SLOT_14 0 CSD_SLOT_15 0 CSD_SLOT_16 0 CSD_SLOT_17 0 CSD_SLOT_18 0 CSD_SLOT_19 0 CSD_SLOT_2 2 CSD_SLOT_20 0 CSD_SLOT_21 0 CSD_SLOT_22 0 CSD_SLOT_23 0 CSD_SLOT_24 0 CSD_SLOT_25 0 CSD_SLOT_26 0 CSD_SLOT_27 0 CSD_SLOT_28 0 CSD_SLOT_29 0 CSD_SLOT_3 3 CSD_SLOT_30 0 CSD_SLOT_31 0 CSD_SLOT_32 0 CSD_SLOT_33 0 CSD_SLOT_34 0 CSD_SLOT_35 0 CSD_SLOT_36 0 CSD_SLOT_37 0 CSD_SLOT_38 0 CSD_SLOT_39 0 CSD_SLOT_4 4 CSD_SLOT_40 0 CSD_SLOT_41 0 CSD_SLOT_42 0 CSD_SLOT_43 0 CSD_SLOT_44 0 CSD_SLOT_45 0 CSD_SLOT_46 0 CSD_SLOT_47 0 CSD_SLOT_48 0 CSD_SLOT_49 0 CSD_SLOT_5 5 CSD_SLOT_50 0 CSD_SLOT_51 0 CSD_SLOT_52 0 CSD_SLOT_53 0 CSD_SLOT_54 0 CSD_SLOT_55 0 CSD_SLOT_56 0 CSD_SLOT_57 0 CSD_SLOT_58 0 CSD_SLOT_59 0 CSD_SLOT_6 6 CSD_SLOT_60 0 CSD_SLOT_61 0 CSD_SLOT_62 0 CSD_SLOT_63 0 CSD_SLOT_7 0 CSD_SLOT_8 0 CSD_SLOT_9 0 PRESCALER_CH16 0 PRESCALER_CH8 0 REFSEL Internal VREF USE_CH0 1 USE_CH1 1 USE_CH10 0 USE_CH11 0 USE_CH12 0 USE_CH13 0 USE_CH14 0 USE_CH15 0 USE_CH16 0 USE_CH2 1 USE_CH3 1 USE_CH4 1 USE_CH5 1 USE_CH6 1 USE_CH7 0 USE_CH8 0 USE_CH9 0 USE_TSD 0 VREF 3.0

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clk_0

clock_source v14.1

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)