ST2110 10G Tx IP Package / ST2110 10G Rx IP Package

SMPTE® ST2110 is the Video/Audio/Ancillary over IP*1 standards suite for Professional media industries, which contributes the movement from SDI to IP-based broadcasting applications. Macnica offers SMPTE® ST2110 IP*2 product as an IP-based solution for broadcasting systems. It consists of ST2110 Hardware IP*2 for Intel® SoC FPGA implementation, ST2110 Software Development Kit, and reference design.

*1: Internet Protocol
*2: Intellectual Property

1.  ST2110 Hardware IP (Tx and Rx)

Features and Specifications

Supported SMPTE Family

  • ST2110-10
  • ST2110-20
  • ST2110-21 (planning)
  • ST2110-30
  • ST2110-31 (planning)
  • ST2110-40
  • ST2022-7
  • ST2022-8 (planning)
  • RP2110-23(planning)

Supported devices

  • Intel® Arria 10 SoC (For 10G Base)
  • Intel® Stratix 10 SoC Type (Planning For 10/25G Base)

ST2110 Tx/Rx IP Block Diagram

ST2110 Tx/Rx IP Block Diagram

2.  ST2110 Software Development Kit

ST2110 SDK

  • Macnica Broadcast Library
    • ST2059 Protocol Stack
    • IGMP Control
    • SDP Management
    • Hardware Control
  • Device Driver Package
    • Hardware Access for each FPGA design blocks

NMOS Adapter Library (Option)

  • Software component which communicates with 3rd party NMOS software

Software Development Environment

  • Linux Kernel: socfpga-4.9.78 -ltsi*
  • Boot Loader: U Boot 2014.10*
  • File System: Angstrom v2015.12*
  • Toolchain: Linaro gcc arm -linux -gnueabihf 5.2
  • Board: Intel® Arria 10 SoC Development Kit

* Same environment used in Rocket Board A10 GSRD v17.1

ST2110 Software Block Diagram

ST2110 Software Block Diagram

3.  System Evaluation Environment

System Evaluation Environment


4.  Deliverables

ST2110 Hardware IP (Tx / Rx)

  • Encrypted RTL for Quartus
  • Encrypted simulation model for ModelSim
  • License File for Quartus

ST2110 Software Development Kit

  • Broadcast Core Engine
  • Broadcast Application Library
  • NMOS Adapter Library (Optional component)


  • User’s Manual
  • Implementation Guideline
    • About Reference design
    • Intel® Core Implementation Guide (XCVR, PLL, etc.)
    • Simulation Guide
    • Software Flow

Reference Design

  • HW : Verilog base Reference design
  • SW : Sample Device Driver
  • SW : Sample CUI Application

Media over IP Demonstration


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