Graphic Controller IP

The Graphic Controller IP synthesizes an input video with graphics in real time. Users can easily implement OSD to display a startup logo, menu screen, text, etc.


  • Screen synthesis with a single background video layer (input video) and up to four graphic layers
  • Inter-layer overlay and α-blending (layers overlaid with specified transparency)
  • Color palette supporting up to 65,536 colors
  • Rectangle and Line drawing
  • Existing prepared graphics and graphics created by the IP can be synthesized as a graphic layer
  • Bit-BLT Function (graphic data transfer within VRAM)
  • DMA graphic data from external memory to VRAM.
  • Compatibility with Avalon interface allows an easy incorporation into Qsys


Item Specifications
Background Image Bit Width Per Color Plane 6, 8, 10, 12 bits
Number of Color Planes 3
Color Format RGB, YUV
Number of Vertical/Horizontal Pixels 4095 pixels maximum
Interface Avalon-ST
Graphic Layer Number of Graphic Layers 4 layers maximum
Layer Zoom Factors 1X, 2X, 3X, 4X
Color Format αRGB, αYUV
α Blending Gradations 256 gradations maximum
Vertical and Horizontal Display Size 4095 pixels maximum
Draw Functions Primitive Drawing Rectangles and lines
Bit-BLT Function 15 modes

Supported Devices

  • Cyclone IV/V
  • Arria V
  • Stratix IV/V

* Please contact Macnica sales department for information about other devices.


  • Encrypted RTL (Verilog HDL)
  • User's manual

Device Resource Utilization

Common Settings: 

  • Per color plane bits: 8
  • layers: 4
  • memory controller and its interface bus size: 128 bits
Color Palette Draw Functions DMA Function Stratix V Cyclone V
ALMs Registers Block Memory bits ALMs Registers Block Memory bits
Yes No No 8,037 8,952 208,512 8,211 9,047 208,512
No Yes Yes 10,219 12,133 305,408 10,568 12,243 305,408
Yes Yes No 12,897 12,424 224,896 13,231 12,417 224,896
Yes Yes Yes 13,917 13,156 233,088 14,254 13,271 233,088

*  The values in the above table are based on an implementation example. There may be some variation depending on the user's system configuration.

Example FPGA Configuration


For more information: