Image Rotation IP

Image Rotation IP rotates video 90, 180, or 270 degrees, and performs frame rate conversion. The video interface and memory controller interface of this IP use Avalon interface. Users can easily incorporate the IP into an FPGA design using Qsys.


  • Rotates input video 90, 180, or 270 degrees.
  • Supports Frame rate conversion
  • Uses DDR2/DDR3 SDRAM. Bank Interleave enables efficient utilization of memory bandwidth.


Item Specifications Remarks
Video Format Vertical and Horizontal Image Size 96 to 2047 pixels each Pixel clock frequency depends on the FPGA used.
Bit Width Per Color 6, 8, 10, 12 bit Set as a static parameter during logic synthesis.
Number of Colors Per Pixel 1 or 3 colors Set as a static parameter during logic synthesis.
Color Format YUV444, RGB
Scan Format Progressive
Video Processing Functions Video Rotation Functions 90° right, 180°,
90° left (270° right)
Frame Rate Conversion Yes
Frame Memory Memory Type DDR2/DDR3 Uses Altera Memory Controller (Half Rate Mode).
Data Width 16 bit, 32 bit
Number of Bursts 8 Burst
Number of Banks 4, 8 Bank Lower performance with four-bank product.
Page Size 512, 1024, 2048 Word Limited by image size.


Supported Devices

  • Cyclone IV/V
  • Arria V/10
  • Stratix IV/V

* Please contact Macnica sales department for information about other devices.


  • Encrypted RTL (Verilog HDL)
  • User’s manualDevice Resource Utilization

Device Resource Utilization

Bit Width Per Color Number of Colors Per Pixel Memory Controller and Interface Width Cyclone V Stratix V
ALMs Registers Block
ALMs Registers Block
8 3 64 bit 1,412 2,220 655,360 1,423 2,133 655,360
128 bit 2,050 2,988 1,179,648 2,043 2,912 1,179,648

*  The values in the above table are based on an implementation example. There may be some variation depending on the user’s system configuration.

Example FPGA Configuration


For more information: