MECHATROLINK-Ⅲ IP is an FPGA IP in conjunction with CPU to implement the capability to communicate with any MECHATROLINK-Ⅲ products instantly.
- The IP is compatible with JL-100 communication ASIC incorporating both Master and Slave functions of MECHATROLINK-Ⅲ.
- The IP supports all required functions for MECHATROLINK-Ⅲ communication which can be set by external pins and/or CPU.
|Transmission Bytes (For data)||8/16/32/48/64|
|Maximum communication terminals||master：1
|Maximum transmission distance||100m to next terminal|
|Minimum transmission distance to next terminal||20cm|
|Connection topology||Cascade / Star|
|Cyclic / Event Driven||Available|
|Retry function||62 max. trials|
|Slave to monitor the other terminals||Available|
- Cyclone V
Please contact Macnica sales department for information about other devices.
- IP (Netlist Format)
- Reference Design
- User’s Manual
Device Resource Utilization
|Items||Master||Slave||Master & Slave|
|Total block memory bits||459776||459776||459776|
System Configuration Example