SLVS-EC v3.0/3.1 Rx IP
Next-generation CMOS image sensor interface, SLVS-EC v3.0/3.1, is implemented in FPGAs
Overview
SLVS-EC v3.0/3.1 Rx IP is an interface IP core that runs on Altera® FPGAs. Using this IP, you can quickly and easily implement products that support the latest SLVS-EC standard v3.1. You will also receive an "Evaluation kit" for early adoption.
- Altera® FPGAs can receive signals directly from the SLVS-EC Interface.
- Compatible with the latest SLVS-EC Specification Version 3.1.
- Supports powerful De-Skew function. Enables board design without considering Skew that occurs between lanes.
- "Evaluation kit” is available for speedy evaluation at the actual device level.
Overview of SLVS-EC Standard
- SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock) is an interface standard for high-speed & high-resolution image sensors developed by Sony Semiconductor Solutions Corporation.
- The SLVS-EC standard is standardized by JIIA (Japan Industrial Imaging Association).
Features
- SLVS-EC Specification Version 1.2/2.0/3.0 and the latest 3.1 are supported.
- Provides various functions defined in the SLVS-EC Link Layer.
- Selectable 32 or 64 pixel for output interface
- Supports 8, 10, 12, 14, 16 bit/pixel
- Realizes transfer with less overhead compared to conventional ANSI 8b10b by taking advantage of GCC (Gigabit Channel Coding) features added in the latest SLVS-EC Version 3.0/3.1.
- Supports error correction using Error Correction Code (ECC)
- Supports Byte to Pixel conversion in 1, 2, 4, 6, and 8 lane configurations.
- Header analysis and payload error detection.
- Compile options allow removal of unnecessary functions.
Specifications
Supported FPGA
Altera® FPGA
- Arria® 10 FPGA
- Agilex™ 7 FPGA
- Agilex™ 5E(GroupB)
Evaluation Kit: Luminous IMX537 SLVS-EC Sensor EVM Kit
For evaluation kit, please see here.
Using Evaluation Kit
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