V-by-One® HS Tx IP / V-by-One® HS Rx IP

High-speed serial interface compliant with V-by-One^® HS standard

V-by-One^® HS IP is an IP to achieve V-by-One HS high-speed video interface technology. V-by-One^® HS is a standard for next-generation high-speed interface technology developed by THine Electronics for image and video equipment requiring higher frame rates and higher resolutions. Implementing the V-by-One HS IP in Altera FPGA reduces the number of signals compared with conventional LVDS interfaces, which greatly reduces product cost.

Features

• Achieves 4-Gbps maximum transmission rate per lane (however, depends on the FPGA used)
• Supports custom video formats as well as VESA, SMPTE, and other standardized formats
• Supports flexible multi-lane designs in accordance with user's total transmission rate requirement
• Self-check function (FieldBET) to test connectivity between transmitter and receiver IPs

Specifications

Supported Devices

• Cyclone^® V GX/GT
• Cyclone 10 GX
• Arria^® V GX
• Arria 10 GX
• Stratix^® V GX
• Stratix 10 (H/L-Tile)

          * Please contact Macnica sales department about other devices.

Deliverables

• Encrypted RTL (Verilog HDL)
• Reference design
• Simulation environment (For ModelSim)
• User's manual
• Reference design user's guide

Device Resource Utilization

*  The values in the above table are based on an implementation example. There may be some variation depending on the user’s system configuration.Configuration Diagram

Configuration Diagram

Evaluation Board