SLVS-EC Rx IP
Next generation Sony CMOS image sensor interface
SLVS-EC Rx IP provides SLVS-EC interface for Altera FPGA to receive image sensor data. SLVS-EC is Sony’s upcoming high-speed interface for next-generation high-resolution CMOS image sensors. This standard is tolerant of lane-to-lane skew because of embedded clock technology, so that it makes a board level design very easy in terms of high-speed and long distance transmission.
- Compliant with SLVS-EC Specification Version 1.2/2.0
- Supports various functions defined by the SLVS-EC Link layer (Altera PCS/PMA is used as Physical layer)
- Supports Byte-to-Pixel conversion for various lane-configurations
- Supports Header analysis and Payload error detection
|Number of Lanes||1, 2, 4, 6, 8|
|Baud Grade||1, 2, 3*|
|Bit per Pixel||8, 10, 12, 14, 16|
|Dynamic Mode Change||Supported|
|Multiple Stream||If needed|
* Baud Grade 3 is supported by only after 10 series.
* CRC: The operating frequency may not be achievable depending on the speed grade, number of lanes, and other factors of the FPGA used.
* Please contact Macnica sales department about unsupported functions and limitations.
- Cyclone V GX
- Cyclone 10 GX
- Arria 10 GX
* Please contact Macnica sales department about other devices.
- Encrypted RTL (Verilog HDL)
- Reference design
- Simulation environment (For ModelSim)
- User's manual, Reference manual, Simulation manual
Device Resource Utilization
Resource Utilization for 8lane full configuration (including both Transceiver and IP)
|Items||Cyclone® V GX||Arria® 10 GX|
|w/o ECC||w/ECC||w/o ECC||w/ECC|
|Total block memory bits||4096||13312||2560||11776|
* The above values are estimated resource utilization of the IP and Transceivers. They may vary depending on your system configuration.
Evaluation / Demonstration
This IP can be evaluated and demonstrated using our EasyMVC Machine Vision Camera Development Kit.