SLVS-EC Rx IP

Next generation Sony CMOS image sensor interface

SLVS-EC Rx IP provides SLVS-EC interface for Altera FPGA to receive image sensor data. SLVS-EC is Sony’s upcoming high-speed interface for next-generation high-resolution CMOS image sensors. This standard is tolerant of lane-to-lane skew because of embedded clock technology, so that it makes a board level design very easy in terms of high-speed and long distance transmission.

Features

• Compliant with SLVS-EC Specification Version 1.2/2.0
• Supports various functions defined by the SLVS-EC Link layer (Altera PCS/PMA is used as Physical layer)
• Supports Byte-to-Pixel conversion for various lane-configurations
• Supports Header analysis and Payload error detection

Specifications

* Baud Grade 3 is supported by only after 10 series.

* CRC: The operating frequency may not be achievable depending on the speed grade, number of lanes, and other factors of the FPGA used.

* Please contact Macnica sales department about unsupported functions and limitations.

Supported Devices

• Cyclone V GX
• Cyclone 10 GX
• Arria 10 GX

* Please contact Macnica sales department about other devices.

Deliverables

• Encrypted RTL (Verilog HDL)
• Reference design
• Simulation environment (For ModelSim)
• User's manual, Reference manual, Simulation manual

Device Resource Utilization

Resource Utilization for 8lane full configuration (including both Transceiver and IP)

*  The above values are estimated resource utilization of the IP and Transceivers. They may vary depending on your system configuration.

Evaluation / Demonstration

This IP can be evaluated and demonstrated using our EasyMVC Machine Vision Camera Development Kit.